Process and device modeling for integrated circuit design

Process and device modeling for integrated circuit design

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no. L. 110 Fig. A. Prismatic punching of dislocation loops by an Si02 precipitate in a silicon matrix. P:ppt with (010) habit plane, aamp;R:ppt with (100) habit plane. Prismatic loops: PA, (a/2) |llOJ (IlO); PB, (a/2) | Oil | (Oil); PC, (a/2) |llO| (110); RD, ( a/2)anbsp;...


Title:Process and device modeling for integrated circuit design
Author: Fernand van de Wiele, Walter L. Engl, Paul G. Jespers
Publisher:Noordhoff International Publishing - 1977
ISBN-13:

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